1. Field of the invention
The present invention concerns complex integrated circuits, and more particularly microprocessors, that are circuits capable of carrying out not only a single well defined function but a whole variety of different functions. Instructions, in the form of coded signals received by the microprocessor, determine the functions to be carried out. The succession of the instructions received determines the sequence of a complex digital processing operation carried out by the microprocessor on date also received at its input.
Each instruction received is stored in an instruction register during the performance of the work corresponding to this instruction. An instructions sequencer causes to correspond to a determined instruction, i.e. to a group of well defined binary signals, a group of control signals appearing on the control lines at the output of the sequencer. These control lines are connected to logic gates, registers or other elements of the circuit. Each instruction thus acts in an unique manner upon a group of circuit elements of the microprocessor. The role of the sequencer is to transform the instructions into signals for controlling the different parts of the microprocessor.
The sequencer thus firstly has a decoding function : transformation of a group of binary signals (the instruction) into a group of control signals; each instruction generally activates several control lines and reciprocally a single control line can be activated by several different instructions.
But, furthermore, the sequencer must establish the performance step of the instruction; in fact, the carrying out of an instruction can lead for example to opening a logic gate then loading a register, etc... The control signals generated by the sequencer must thus appear according to a logic sequence in several steps or phases and not in a single step or phase.
This is the reason why an instructions sequencer generally comprises an instructions decoding circuit followed by a circuit for determining the activation steps of the signals issuing from the decoding circuit.
The present invention concerns more particularly the constitution of this circuit for determining the steps for activating the control lines of the microprocessor.
The usual solution for producing this circuit for determining the activation steps consists in placing at the output of the instructions decoding circuit AND and OR (or NAND or NOR if this appears more practical) gates receiving on the one hand the outputs of the decoding circuit and receiving on the other hand signals corresponding to the various steps of an instruction cycle. The outputs of these gates or groups of gates constitutes control lines activated at well defined steps.
In order to reduce the bulk of this circuit for step determination, and also to render its conception and its topology or lay-out easier between the outputs of the instructions decoding circuit and the outputs of the sequencer itself, without rendering manufacturing more difficult, the production of the circuit for step determination in a particularly simple matrix form is proposed herebelow.
According to the invention, the circuit for determining the steps is essentially constituted by a matrix of transistors arranged in lines and columns, transistors being present at all the lines and columns intersections, the transistors of a single line being placed in series between an output of the instructions decoding circuit corresponding to this line and an output of the circuit for step determination also corresponding to this line, the transistors of a single column all being controlled simultaneously by a signal corresponding to a respective step and the transistors of the other columns being controlled by signals corresponding to other steps, certain transistors being of the depleted type in order to be coductive whatever the control signal applied to the column of which they form part and certain transistors being of the enriched type in order to be conductive only during the step corresponding to the column of which they form part.
More generally, the invention concerns a matrix of logic gates (programmable by mask) that comprises transistors arranged in lines and columns, the transistors being present at all the lines and columns intersections, the transistors of a single line being placed in seriess between a matrix input corresponding to this line and a matrix output also corresponding to this line, the transistors of a single column all having their grids connected to a matrix input corresponding to this column and the transistors of the other columns having their grids connected to other matrix inputs corresponding to the other columns, certain transistors being of the depleted type in order to be conductive whatever the logic level applied to their grid and other transistors being of the non-depleted type in order to be conductive for a logic level applied to their grid and to be blocked for a complementary logic level applied to their grid.